In an attempt to improve the performance, reliability and density of fully integrated ULSI (ultra-large scale integration) interconnects, the microelectronics industry has recently begun migrating away from the use of aluminum (Al) and/or its alloys for the ULSI interconnects. As such, advanced dual damascene processes have begun using copper (Cu) as the material of choice because copper has high conductivity, extremely low resistivity (about 1.7 μΩcm) and good resistance to electromigration. Unfortunately, copper diffuses rapidly through silicon dioxide (SiO2) or other interlayer dielectrics, such as polyimides and parylenes, and copper diffusion can destroy active devices, such as transistors and capacitors, formed in the IC substrate. In addition, metal adhesion to the underlying substrate materials must be excellent to form reliable interconnect structures but the adhesion of copper to interlayer dielectrics, particularly to SiO2, is generally poor.
Another problem associated with dual damascene processing is the cost and complexity of the process. Advanced copper dual damascene processes include a two-step sequential mask/etch process to form a two-level structure, such as a via connected to a metal line situated above the via. As illustrated in FIG. 1, a known copper dual damascene process as applied to interconnect formation begins with the deposition of a first insulating layer 14 over a first level interconnect copper layer 12, which in turn is formed over or within a semiconductor substrate 10. A second insulating layer 16 is next formed over the first insulating layer 14. An etch stop layer 15 is typically formed between the first and second insulating layers 14, 16. The second insulating layer 16 is patterned by photolithography with a first mask (not shown) to form a trench 17 corresponding to a copper line of a second level interconnect. The etch stop layer 15 prevents the upper level trench pattern 17 from being etched through the first insulating layer 14.
As illustrated in FIG. 2, a second masking step followed by an etch step are applied to form a via 18 through the etch stop layer 15 and the first insulating layer 14. After the etching is completed, both the trench 17 and the via 18 are filled with copper material 20, as illustrated in FIG. 3. Typically, the copper material 20 undergoes a chemical mechanical polishing (CMP) step to remove any copper material from above the second insulating layer 16 and to form, therefore, a copper damascene structure as illustrated in FIG. 4. The CMP step leaves the copper damascene structure 25 with a copper planarized surface for subsequent metallization to build multi-level interconnects.
If desired, a second etch stop layer (not shown) may be formed between the substrate 10 and the first insulating layer 14 during the formation of the copper damascene structure 25. In any event, and in contrast to a single damascene process, the via and the trench are simultaneously filled with metal. Thus, although copper dual damascene process is more advantageous over the copper single damascene process, one big disadvantage remains the high number of sequential photoresist/mask/etch steps and etch-stop layers which, as described above, are conventionally used in damascene processing and which increase the fabrication cost and reduce the production yield. Another disadvantage is that copper deposition methods for conventional damascene processes employ a large amount of high-purity copper material, of which a considerable amount is removed and wasted by the CMP process described above with reference to FIGS. 3-4. Thus, even the dual damascene processing is very expensive and entails a large number of processing steps.
Accordingly, there is a need for an improved and simplified copper damascene process which reduces production costs and increases productivity. There is also a need for a method of increasing the adhesion of copper to underlying damascene layers as well as a method of decreasing copper diffusion in such layers.